1. Field of the Invention
The present invention relates to a circuit configuration for detecting a level of a predetermined voltage, in particular, of a power supply voltage in a semiconductor device.
2. Description of the Background Art
Since a semiconductor device has a predetermined rated value of a power supply voltage, it is required that the power supply voltage be within a predetermined range for stable operation. An extremely high operating power supply voltage causes dielectric breakdown and the like of circuit elements, while an extremely low operating power supply voltage does not contribute to desired operating characteristics and stable operation of a circuit, thereby impairing reliability of a semiconductor device.
Therefore, as shown in FIG. 5, a circuit for monitoring the level of the power supply voltage is provided in a semiconductor device.
FIG. 5 is a diagram showing the entire configuration of a general semiconductor device. A semiconductor device 100 includes a power supply voltage level detecting circuit 110 for detecting a level of an externally applied power supply voltage Vcc and a function circuit 120 for operating with power supply voltage Vcc as an operating power supply voltage to implement a desired function.
The power supply voltage level detecting circuit 110 generates an abnormality detecting signal, applies the signal to the function circuit 120 and stops or resets operation of the function circuit 120, when the level of the power supply voltage Vcc attains a predetermined level.
The function circuit 120 may be of any type as far as it is of a type which processes signals digitally. The function circuit 120 may also be a circuit that operates with an internal step-down voltage of a stepped down power supply voltage Vcc as an operating power supply voltage.
FIG. 6 is a diagram showing a specific configuration of the power supply voltage level detecting circuit shown in FIG. 5. Referring to FIG. 6, the power supply voltage level detecting circuit 110 includes a reference voltage generating circuit 4 for generating a reference voltage of a constant voltage level independent of the voltage level of the power supply voltage Vcc, an inverter circuit 7a for receiving an output of the-reference voltage generating circuit 4, and an inverter circuit 7b for receiving an output of the inverter circuit 7a.
The reference voltage generating circuit 4 includes a p channel MOS (insulated gate type field effect) transistor 2 connected between a node (a power supply line 30) receiving the power supply voltage Vcc and a reference voltage output node 8, an n channel MOS transistor 1a provided between the reference voltage output node 8 and a node 31, and n channel MOS transistors 1b, 1c and 1d connected in series between node 31 and the other power supply potential (which is usually a ground potential and hereinafter simply referred to as a ground potential) Vss and each serving as a diode. The transistor 2, having its gate connected to the ground potential Vss, serves as a resistance. The transistor 1a receives a reset signal .phi.R at its gate, is rendered conductive only when the reset signal .phi.R is at a high level, and connects the node 31 to the reference voltage output node 8 electrically.
Transistors 1b to 1d have respective gates connected to respective drains, and each serves as a diode which decreases the voltage by its threshold voltage Vthn. The on-resistance of the transistor 2 is rendered relatively large. The on-resistance of the transistor 1a is rendered sufficiently small. Therefore, a reference voltage independent of the power supply voltage Vcc of voltage level Vss+3.multidot.Vthn is generated from the reference voltage output node 8. The reset signal .phi.R is at a high level in normal operation, and the transistor 1a is provided to reduce power consumption by rendering a current flow path in the reference voltage generating circuit 4 nonconductive/conductive.
The inverter circuit 7a includes complementarily connected p channel MOS transistor 22a and n channel MOS transistor 21a between the power supply line 30 and the ground potential Vss. The inverter circuit 7b includes complementarily connected p channel MOS transistor 22b and n channel MOS transistor 21b between the power supply line 30 and the ground potential Vss. Transistors 22a and 21a receive at their gates a reference voltage which appears at the output node 8 of the reference voltage generating circuit 4. Transistors 22b and 21b receive at their gates a voltage which appears at the output node 10 of the inverter circuit 7a. A voltage level detecting signal indicating whether or not the power supply voltage Vcc has attained a predetermined level is generated from the output node 11 of the inverter circuit 7b. Operation will now be described.
FIG. 7 is a graph showing dependency on the power supply voltage of input/output characteristics of an inverter circuit. Referring to FIG. 7, the ordinate shows an input voltage of the inverter circuit, and the abscissa shows an output voltage of the same. As shown in FIG. 7, the inverter circuit has its input logic threshold voltage (the level identifying high and low levels of an input signal) increased in accordance with the power supply voltage Vcc. Referring to FIG. 7, the input logic threshold voltage (hereinafter simply referred to as a threshold voltage) is VT1 when the power supply voltage Vcc is 5 V, the threshold voltage is VT2 when the power supply voltage Vcc is 6 V, and the threshold voltage is VT3 when the power supply voltage Vcc is 7 V. In general, in a CMOS inverter circuit of a p channel MOS transistor and an n channel MOS transistor, the relation between the threshold voltage VT and the power supply voltage Vcc is given by the following formula (1). ##EQU1##
In the above formula (1), Vthp and Vthn indicate threshold voltages of a p channel MOS transistor and an n channel MOS transistor, respectively. Wn and Ln indicate gate width and gate length of an n channel MOS transistor, respectively. Gate length indicates the length of the gate along the channel direction between the source and drain of an MOS transistor, and gate width indicates the width of the source and drain impurity regions in the direction orthogonal to the gate length.
Wp and Lp indicate gate width and gate length, respectively, of a p channel MOS transistor. .beta.on and .beta.op are constants proportional to capacitance of a gate insulating film per unit area, which are usually on the order of: EQU .beta.on:.beta.op=2:1
As apparent from the formula (1), the threshold voltage VT of an inverter circuit increases in accordance with the power supply voltage Vcc.
FIG. 8 shows dependency on a power supply voltage of an output of each circuit shown in FIG. 6. Referring to FIG. 8, the ordinate shows power supply voltage Vcc, and the abscissa shows voltage.
A voltage given by the sum of a forward drop voltage across transistors 1b to 1d and the ground potential Vss is applied to the reference voltage output node 8 of the reference voltage generating circuit 4. In other words, a voltage of 3.multidot.Vthn is supplied as an output from the reference voltage output node 8, where Vss is 0 V. The threshold voltage Vthn of MOS transistors 1b to 1d is considered to be almost constant independent of the operating power supply voltage Vcc (strictly speaking, the threshold voltage subtly varies in response to variation of operating power supply voltage Vcc due to the influence of back gate bias and the like, but this variation of the threshold voltage is considered to be negligible).
Therefore, as shown by curve I in FIG. 8, a constant voltage of approximately 4 V is supplied as an output from the reference voltage output node 8.
The inverter circuit 7a receives a reference voltage which appears at the reference voltage output node 8. The determination by inverter circuit 7a between high and low levels of the reference voltage which is supplied as an output from the reference voltage output node 8 is made in accordance with the level of the power supply voltage Vcc. The level of the reference voltage (4 V) supplied as an output from the reference voltage output node 8 is now assumed to be larger than threshold voltages VT1 and VT2 of the inverter circuit shown in FIG. 7 and smaller than threshold voltage VT3 of the same.
Referring now to FIG. 8, curve I shows voltage which appears at the reference voltage output node 8 of the reference voltage generating circuit 4. Curve II shows voltage change which appears at the output node 10 of the inverter circuit 7a. Curve III shows voltage change which appears at the output node 11 of the inverter circuit 7b.
The reference voltage which appears at the output node 8 of the reference voltage generating circuit 4 is constant, approximately 4 V, as shown by curve I. In a state where the power supply voltage Vcc is low, i.e., 5 V or 6 V, the reference voltage which appears at the reference voltage output node 8 of the reference voltage generating circuit 4 is higher than the threshold voltage (indicated by curve VT in FIG. 8) of the inverter circuit 7a. Therefore, the inverter circuit 7a determines the reference voltage from the reference voltage output node 8 to be at a high level to supply the output node 10 with a low-level signal as an output. The inverter circuit 7b supplies the output node 11 with a high-level signal as an output in accordance with the low-level signal from the inverter circuit 7a. Since the high-level signal output from the inverter circuit 7b is applied through the p channel MOS transistor 22b, the voltage level is the level of the power supply voltage Vcc.
As the power supply voltage Vcc increases, the threshold voltage VT of the inverter circuit 7a increases as shown by curve VT in FIG. 8. When the power supply voltage Vcc exceeds a certain voltage level (for example, 7 V), the reference voltage from the output node 8 of the reference voltage generating circuit 4 becomes lower than the threshold voltage VT of the inverter circuit 7a. In this case, the inverter circuit 7a determines the reference voltage of the output node 8 to be at a low level to supply the output node 10 with a high-level signal as an output. The inverter circuit 7b supplies a low-level signal as an output in response to the high-level signal provided from the inverter circuit 7a. The voltage level of the high-level output signal of the inverter circuit 7a increases as the level of the power supply voltage Vcc increases.
Since the inverter circuit 7b receives an output signal of the inverter circuit 7a to further amplify the signal amplified at the inverter circuit 7a, the output response characteristic thereof becomes faster than that of the inverter circuit 7a.
As a result, since a level detecting signal which appears at the output node 11 of the inverter circuit 7a falls from a high level to a low level when the power supply voltage Vcc attains, for example, the level of 7 V, it is possible to detect that the power supply voltage Vcc has attained a predetermined voltage level by observing this change.
A conventional power supply voltage level detecting circuit utilizes change of the threshold voltage of an inverter circuit depending on the power supply voltage. When power supply voltage dependency characteristics of the threshold voltage of the inverter circuit change significantly, since the detected level of power supply voltage changes considerably, it becomes impossible to detect a desired level of power supply voltage. This is why it is necessary to precisely control the threshold voltage of an inverter circuit.
The threshold voltage of an inverter circuit, as shown in the formula (1), depends on various parameters such as threshold voltage, gate width, gate length, size and the like of a transistor, which are components of the formula (1). These parameters are subjected to variation during the manufacturing processes. Therefore, there arises a problem that it is difficult to give precisely desired power supply voltage dependency characteristics to the threshold voltage of an inverter circuit.